Indent XML output for TT assembly instructions

Indentation for TTX XMLF is 2 spaces. I chose 4 spaces for indentation of instructions to make it more noticeable. I hope it’s not a problem, because assembly code lines are usually very short.
This commit is contained in:
Jens Kutilek 2017-01-23 16:10:48 +01:00 committed by GitHub
parent 3ec651ee22
commit bec499ac05

View File

@ -194,6 +194,8 @@ _whiteRE = re.compile(r"\s*")
_pushCountPat = re.compile(r"[A-Z][A-Z0-9]*\s*\[.*?\]\s*/\* ([0-9]+).*?\*/")
_indentRE = re.compile("^FDEF|IF|ELSE\[ \]\t.+")
_unindentRE = re.compile("^ELSE|ENDF|EIF\[ \]\t.+")
def _skipWhite(data, pos):
m = _whiteRE.match(data, pos)
@ -248,9 +250,13 @@ class Program(object):
writer.begintag("assembly")
writer.newline()
i = 0
indent = 0
nInstr = len(assembly)
while i < nInstr:
instr = assembly[i]
if _unindentRE.match(instr):
indent -= 1
writer.write(" " + " " * indent)
writer.write(instr)
writer.newline()
m = _pushCountPat.match(instr)
@ -261,13 +267,17 @@ class Program(object):
j = 0
for j in range(nValues):
if j and not (j % 25):
writer.write(" " + " " * indent)
writer.write(' '.join(line))
writer.newline()
line = []
line.append(assembly[i+j])
writer.write(" " + " " * indent)
writer.write(' '.join(line))
writer.newline()
i = i + j + 1
if _indentRE.match(instr):
indent += 1
writer.endtag("assembly")
else:
writer.begintag("bytecode")